1. Field of technology
The present invention relates to a junction-type field effect transistor (hereinafter referred to J-FET for short).
2. Prior Arts
In general, a p-n junction-type field effect transistor is conventionally fabricated by using epitaxial method and thermal diffusion method. FIG. 1 shows a structure of the J-FET fabricated by the epitaxial method. An n-conductivity type silicon layer 2 is made on a p-type silicon substrate 1 by the epitaxial method. And an n-type island region 2 is formed by diffusing p-type isolating regions 3,3. And in the island region 2, a source region 4 and a drain region 5 of n.sup.+ -type are formed. Then a p.sup.+ -type gate region 6 is formed by the thermal diffusion method. Thus, a J-FET is fabricated as shown in FIG. 1. In the J-FET shown in FIG. 1 it is difficult to control thickness of the epitaxial layer 2 formed on the p-type silicon substrate 1 and depth of the gate region 6; in other words it is difficult to control channel thickness "t" in FIG. 1. Therefore, drain current flowing between the source and the drain can not be sufficiently controlled as designed.
To improve this situation it is also proposed that the n-type island region 2 is formed on the p-type substrate by ion implantation. It is known that, the scatter of the drain current in a wafer is reduced from .+-.80% of the ones fabricated by the epitaxial growth method to .+-.20% of the ones by the ion implantation method. But if the island region 2 is formed by the ion implantation, a heat treatment follows thereafter. Therefore, after the heat treatment, the distribution of the donor impurity concentration in the n-type island region 2 has its maximum at the surface part. Accordingly, most of the drain current flows through surface states, which act as recombination centers, and hence output signal has noise due to recombination and surface effect.
As another prior art to reduce surface current, a device comprising i-type (intrinsic) region at the surface thereof is disclosed in the specification of the U.S. Pat. No. 3,656,031 for H.J. Bresee et al. FIG. 2 shows the device, wherein a low concentration region 11 of p-type conductivity is diffused on an n-type silicon substrate. Impurity concentration of the region 11 has its maximum at the surface. Between a source region 13 and a drain region 12, a highly doped diffused gate region 14 of an n.sup.+ -type conductivity is formed. The J-FET thus formed is characterized by comprising a surface region 15 of low impurity concentration p.sup.- -type or of high resistivity intrinsic region (i-layer) which is formed by lowering the surface impurity concentration of the p-type island region 11.
This surface region 15 can be formed, for example,
(i) by using segregation effect of the p-type impurity during thermal oxidation of the substrate material, to obtain the p.sup.- -type layer,
(ii) by diffusing a small amount of n-type impurities, which is opposite to the conductivity type of a channel to obtain the i-type layer,
(iii) by using ion implantation of the p-type impurities to have a concentration peak at a specified depth from the surface and to use the ion-implanted p-type layer as the channel, or
(iv) by using epitaxial process to form the i-type layer at the surface.
The device shown in FIG. 2 is fabricated in such a manner that the channel region of high impurity concentration is formed in the bulk material under the intrinsic or low conductivity region to reduce noise due to surface effect.
In this case, channel current flows inside the bulk material, since the surface region on the channel is p.sup.- -type layer or intrinsic layer. But the channel current is likely affected by the condition of the surface through the surface region 15, and noise source still exists. This situation arises from the fact that owing to smallness of carrier density in the i-type layer or p.sup.- -type layer, the conductivity variation owing to carriers generated at the surface and other carriers generated owing to the effect of ions in an insulation layer on the surface is extremely large. Accordingly, electric field variation by the conductivity variation acts on the channel thereunder, and the noise comes into the channel current.
As clearly shown in the fact that a MOS-type semiconductor device utilizes the surface conductivity modulation, the conductivity variation in the i-type or p.sup.- -type layer is large. This variation affects the channel region thereunder and therefore it is impossible to completely eliminate the adverse effect at the surface. That means, it is not preferable to form the layer of low impurity concentration or of intrinsic type at the surface part above the channel.